Recent radio architectures, such as Wireless Gigabit Alliance (WiGig) and 5th generation mobile networks (5G), require analog-to-digital converters with bandwidth beyond 1 GigaHertz (GHz) and effective number of bits (ENOB) of 6-to8 bits while retaining excellent power efficiency for long battery life.
Therefore, many time-interleaved successive approximation analog-to-digital converters are used in a distributed sampling scheme, leaving the timing-skew problem to be resolved by calibration.
Only a few timing-skew calibration algorithms have been reported for interleaved analog-to-digital converters (ADCs) to correct timing errors in the analog domain or in the digital domain.
With reference to Taiwan patent No. 201406070, various multi-lane ADCs are disclosed that substantially compensate for impairments present within various signals that result from various impairments, such as phase offset, amplitude offset, and/or DC offset to provide some examples, such that their respective digital output samples accurately represent their respective analog inputs. Generally, the various multi-lane ADCs determine various statistical relationships, such as various correlations to provide an example, between these various signals and various known calibration signals to quantify the phase offset, amplitude offset, and/or DC offset that may be present within the various signals. The various multi-lane ADCs adjust the various signals to substantially compensate for the phase offset, amplitude offset, and/or DC offset based upon these various statistical relationships such that their respective digital output samples accurately represent their respective analog inputs.
The drawback of analog correction includes a feedback-induced stability hazard and jitter introduced by the controlled delay line. Digital-domain correction takes advantage of technology scaling but the complex slope-extraction filter limits signal bandwidth.